Integrated circuits (ICs) typically contain one or more functional logic blocks (FLBs). ICs are often tested before they are incorporated into an electronic assembly, in order to verify that each component of each FLB on the IC functions properly, and to verify that the input/output (I/O) terminals of each IC operate correctly within specified timing parameters or timing margins.
In testing ICs, it is known to use source synchronous data transfer on busses interconnecting FLBs within a single IC or within an electronic assembly comprising multiple ICs. In a source synchronous interface, a receiving I/O buffer captures data based upon a strobe clock, or “timing marker,” which is provided by another FLB or a device that is driving the data. The use of digital delay circuits on ICs to assist in centering a strobe signal with respect to a data cell is known in the art.
In order to test whether source synchronous interfaces are operating properly, it is desirable to be able to vary the delay of a digital delay circuit in order to shift a strobe signal across a full data bit cell time. This is desirable in order to measure the effective input latch setup and hold timing. Generally, the strobe signal is shifted by sequentially applying an ever increasing delay to the strobe signal. The phase increment between the delay steps has a granularity that is determined by the delay circuitry.
As device frequencies continue to increase, it is desirable to reduce the granularity between delay steps. Some prior art systems have used BiCMOS (bipolar, complementary metal oxide semiconductor) technologies to achieve relatively small delay step granularities. However, these systems have often included numerous ICs, and accordingly, such systems are expensive and tend to consume large amounts of power.
For the reasons stated above and for other reasons, which will become apparent upon reading and understanding the present specification, there is a significant need in the art for variable-delay circuits and methods of their use, which can produce delayed signals with reduced phase increments between delay steps. In addition, there is a need for variable-delay circuits and methods of their use, which maintain acceptable linearity between successive delay steps. Further needed are variable-delay circuits, which have relatively low IC counts, and which consume relatively small amounts of power.